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| IPD12N03LB G OptiMOS(R)2 Power-Transistor Features * Ideal for high-frequency dc/dc converters * Qualified according to JEDEC1) for target applications * N-channel, logic level * Excellent gate charge x R DS(on) product (FOM) * Superior thermal resistance * 175 C operating temperature * Pb-free lead plating; RoHS compliant Product Summary V DS R DS(on),max ID 30 11.6 30 V m A P-TO252-3-11 Type IPD12N03LB G Package P-TO252-3-11 Ordering Code Q67042-S Marking 12N03LB Maximum ratings, at T j=25 C, unless otherwise specified Parameter Continuous drain current Symbol Conditions ID T C=25 C2) T C=100 C Pulsed drain current Avalanche energy, single pulse Reverse diode dv /dt Gate source voltage4) Power dissipation Operating and storage temperature IEC climatic category; DIN IEC 68-1 I D,pulse E AS dv /dt V GS P tot T j, T stg T C=25 C T C=25 C3) I D=30 A, R GS=25 I D=30 A, V DS=20 V, di /dt =200 A/s, T j,max=175 C Value 30 30 120 64 6 20 52 -55 ... 175 55/175/56 mJ kV/s V W C Unit A Rev. 1.21 page 1 2005-02-03 IPD12N03LB G Parameter Symbol Conditions min. Thermal characteristics Thermal resistance, junction - case SMD version, device on PCB R thJC R thJA minimal footprint 6 cm2 cooling area5) Electrical characteristics, at T j=25 C, unless otherwise specified Static characteristics Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current V (BR)DSS V GS=0 V, I D=1 mA V GS(th) I DSS V DS=V GS, I D=20 A V DS=30 V, V GS=0 V, T j=25 C V DS=30 V, V GS=0 V, T j=125 C Gate-source leakage current Drain-source on-state resistance I GSS R DS(on) V GS=20 V, V DS=0 V V GS=4.5 V, I D=20 A V GS=10 V, I D=30 A Gate resistance Transconductance RG g fs |V DS|>2|I D|R DS(on)max, I D=30 A 30 1.2 1.6 0.1 2 1 A V 2.9 75 50 K/W Values typ. max. Unit 21 10 10 14.1 9.6 1 43 100 100 17.7 11.6 S nA m 1) J-STD20 and JESD22 Current is limited by bondwire; with an R thJC=2.9 K/W the chip is able to carry 50 A. See figure 3 T j,max=150 C and duty cycle D <0.25 for V GS<-5 V 1) 3) 4) 5) 2 Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm (one layer, 70 m thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.21 page 2 2005-02-03 IPD12N03LB G Parameter Symbol Conditions min. Dynamic characteristics Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Gate Charge Characteristics 6) Gate to source charge Gate charge at threshold Gate to drain charge Switching charge Gate charge total Gate plateau voltage Gate charge total, sync. FET Output charge Reverse Diode Diode continous forward current Diode pulse current Diode forward voltage IS I S,pulse V SD T C=25 C V GS=0 V, I F=30 A, T j=25 C V R=15 V, I F=I S, di F/dt =400 A/s 0.93 30 210 1.2 V A Q gs Q g(th) Q gd Q sw Qg V plateau Q g(sync) Q oss V GS=10 V, I D=30 A V DD=15 V, V GS=0 V V DD=15 V, I D=15 A, V GS=0 to 5 V 3 1.6 2.1 4 8 3.2 7 8 4 2.2 3 5 11 9 11 V nC nC C iss C oss Crss t d(on) tr t d(off) tf V DD=15 V, V GS=10 V, I D=15 A, R G=2.7 V GS=0 V, V DS=15 V, f =1 MHz 1000 360 49 6 5 18 2.6 1300 480 74 9 7 27 4 ns pF Values typ. max. Unit Reverse recovery charge Q rr - - 10 nC 6) See figure 16 for gate charge parameter definition Rev. 1.21 page 3 2005-02-03 IPD12N03LB G 1 Power dissipation P tot=f(T C) 2 Drain current I D=f(T C); V GS10 V 60 40 50 30 40 P tot [W] 30 I D [A] 0 50 100 150 200 20 20 10 10 0 0 0 50 100 150 200 T C [C] T C [C] 3 Safe operating area I D=f(V DS); T C=25 C; D =0 parameter: t p 1000 4 Max. transient thermal impedance Z thJC=f(t p) parameter: D =t p/T 10 0.5 limited by on-state resistance 10 s 100 s DC 1 s 1 0.2 0.1 100 Z thJC [K/W] 0.05 I D [A] 0.1 0.02 0.01 single pulse 10 1 ms 0.01 10 ms 1 0.1 1 10 100 0.001 0 0 0 0 0 0 1 10-6 10-5 10-4 10-3 10-2 10-1 100 V DS [V] t p [s] Rev. 1.21 page 4 2005-02-03 IPD12N03LB G 5 Typ. output characteristics I D=f(V DS); T j=25 C parameter: V GS 60 4.5 V 10 V 6 Typ. drain-source on resistance R DS(on)=f(I D); T j=25 C parameter: V GS 24 22 4.1 V 3.5 V 3.8 V 4.1 V 4.5 V 50 20 18 40 3.8 V 16 R DS(on) [m] I D [A] 14 12 10 8 10 V 30 3.5 V 20 3.2 V 6 4 2 0 10 3V 2.8 V 0 0 1 2 3 0 20 40 60 80 100 V DS [V] I D [A] 7 Typ. transfer characteristics I D=f(V GS); |V DS|>2|I D|R DS(on)max parameter: T j 100 8 Typ. forward transconductance g fs=f(I D); T j=25 C 70 60 80 50 60 g fs [S] 40 20 175 C 25 C I D [A] 40 30 20 10 0 0 1 2 3 4 5 0 0 10 20 30 40 50 60 V GS [V] I D [A] Rev. 1.21 page 5 2005-02-03 IPD12N03LB G 9 Drain-source on-state resistance R DS(on)=f(T j); I D=30 A; V GS=10 V 10 Typ. gate threshold voltage V GS(th)=f(T j); V GS=V DS parameter: I D 24 22 20 18 16 200 A 2.5 2 R DS(on) [m] 98 % V GS(th) [V] 14 12 10 8 6 4 2 0 -60 -20 20 1.5 20 A typ 1 0.5 0 60 100 140 180 -60 -20 20 60 100 140 180 T j [C] T j [C] 11 Typ. capacitances C =f(V DS); V GS=0 V; f =1 MHz 12 Forward characteristics of reverse diode I F=f(V SD) parameter: T j 10000 100 25 C, 98% 175 C, 98% Ciss 1000 Coss 175 C 25 C C [pF] I F [A] 100 Crss 10 10 0 5 10 15 20 25 30 1 0.0 0.5 1.0 1.5 2.0 V DS [V] V SD [V] Rev. 1.21 page 6 2005-02-03 IPD12N03LB G 13 Avalanche characteristics I AS=f(t AV); R GS=25 parameter: Tj(start) 100 14 Typ. gate charge V GS=f(Q gate); I D=15 A pulsed parameter: V DD 12 15 V 10 6V 24 V 8 25 C 10 V GS [V] 1000 I AV [A] 100 C 150 C 6 4 2 1 1 10 100 0 0 5 10 15 20 t AV [s] Q gate [nC] 15 Drain-source breakdown voltage V BR(DSS)=f(T j); I D=1 mA 16 Gate charge waveforms 38 V GS 36 34 32 Qg V BR(DSS) [V] 30 28 26 24 22 20 -60 -20 20 60 100 140 180 V g s(th) Q g(th) Q gs Q sw Q gd Q g ate T j [C] Rev. 1.21 page 7 2005-02-03 IPD12N03LB G Package Outline P-TO252-3-11: Outline Footprint: V GS=10 V, I D=30 A Dimensions in mm Rev. 1.21 page 8 2005-02-03 IPD12N03LB G Published by Infineon Technologies AG Bereich Kommunikation St.-Martin-Strae 53 D-81541 Munchen (c) Infineon Technologies AG 1999 All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery teV GS=10 V, I D=30 A nearest Infineon Technologies office in Germany or our Infineon Technologies representatives worldwide (see address list). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact your nearest Infineon Technologies office. Infineon Technologies' components may only be used in life-support devices or systems with the expressed written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.21 page 9 2005-02-03 |
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